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sbidef.h
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1 #pragma once
2 
3 /* SBI Extension IDs */
4 #define SBI_EXT_0_1_SET_TIMER 0x0
5 #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
6 #define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
7 #define SBI_EXT_0_1_CLEAR_IPI 0x3
8 #define SBI_EXT_0_1_SEND_IPI 0x4
9 #define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
10 #define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
11 #define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
12 #define SBI_EXT_0_1_SHUTDOWN 0x8
13 #define SBI_EXT_BASE 0x10
14 #define SBI_EXT_TIME 0x54494D45
15 #define SBI_EXT_IPI 0x735049
16 #define SBI_EXT_RFENCE 0x52464E43
17 #define SBI_EXT_HSM 0x48534D
18 #define SBI_EXT_SRST 0x53525354
19 #define SBI_EXT_PMU 0x504D55
20 #define SBI_EXT_DBCN 0x4442434E
21 #define SBI_EXT_SUSP 0x53555350
22 #define SBI_EXT_CPPC 0x43505043
23 
24 /* SBI function IDs for BASE extension*/
25 #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
26 #define SBI_EXT_BASE_GET_IMP_ID 0x1
27 #define SBI_EXT_BASE_GET_IMP_VERSION 0x2
28 #define SBI_EXT_BASE_PROBE_EXT 0x3
29 #define SBI_EXT_BASE_GET_MVENDORID 0x4
30 #define SBI_EXT_BASE_GET_MARCHID 0x5
31 #define SBI_EXT_BASE_GET_MIMPID 0x6
32 
33 /* SBI function IDs for TIME extension*/
34 #define SBI_EXT_TIME_SET_TIMER 0x0
35 
36 /* SBI function IDs for IPI extension*/
37 #define SBI_EXT_IPI_SEND_IPI 0x0
38 
39 /* SBI function IDs for RFENCE extension*/
40 #define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
41 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
42 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
43 #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x3
44 #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x4
45 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x5
46 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x6
47 
48 /* SBI function IDs for HSM extension */
49 #define SBI_EXT_HSM_HART_START 0x0
50 #define SBI_EXT_HSM_HART_STOP 0x1
51 #define SBI_EXT_HSM_HART_GET_STATUS 0x2
52 #define SBI_EXT_HSM_HART_SUSPEND 0x3
53 
54 #define SBI_HSM_STATE_STARTED 0x0
55 #define SBI_HSM_STATE_STOPPED 0x1
56 #define SBI_HSM_STATE_START_PENDING 0x2
57 #define SBI_HSM_STATE_STOP_PENDING 0x3
58 #define SBI_HSM_STATE_SUSPENDED 0x4
59 #define SBI_HSM_STATE_SUSPEND_PENDING 0x5
60 #define SBI_HSM_STATE_RESUME_PENDING 0x6
61 
62 #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
63 #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
64 #define SBI_HSM_SUSP_PLAT_BASE 0x10000000
65 
66 #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
67 #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
68 #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
69 #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
70 #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | SBI_HSM_SUSP_PLAT_BASE)
71 #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | SBI_HSM_SUSP_BASE_MASK)
72 
73 /* SBI function IDs for SRST extension */
74 #define SBI_EXT_SRST_RESET 0x0
75 
76 #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
77 #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
78 #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
79 #define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
80 
81 #define SBI_SRST_RESET_REASON_NONE 0x0
82 #define SBI_SRST_RESET_REASON_SYSFAIL 0x1
83 
84 /* SBI function IDs for PMU extension */
85 #define SBI_EXT_PMU_NUM_COUNTERS 0x0
86 #define SBI_EXT_PMU_COUNTER_GET_INFO 0x1
87 #define SBI_EXT_PMU_COUNTER_CFG_MATCH 0x2
88 #define SBI_EXT_PMU_COUNTER_START 0x3
89 #define SBI_EXT_PMU_COUNTER_STOP 0x4
90 #define SBI_EXT_PMU_COUNTER_FW_READ 0x5
91 #define SBI_EXT_PMU_COUNTER_FW_READ_HI 0x6
92 
94 #define SBI_PMU_HW_NO_EVENT 0
95 #define SBI_PMU_HW_CPU_CYCLES 1
96 #define SBI_PMU_HW_INSTRUCTIONS 2
97 #define SBI_PMU_HW_CACHE_REFERENCES 3
98 #define SBI_PMU_HW_CACHE_MISSES 4
99 #define SBI_PMU_HW_BRANCH_INSTRUCTIONS 5
100 #define SBI_PMU_HW_BRANCH_MISSES 6
101 #define SBI_PMU_HW_BUS_CYCLES 7
102 #define SBI_PMU_HW_STALLED_CYCLES_FRONTEND 8
103 #define SBI_PMU_HW_STALLED_CYCLES_BACKEND 9
104 #define SBI_PMU_HW_REF_CPU_CYCLES 10
105 #define SBI_PMU_HW_GENERAL_MAX 11
106 
114 #define SBI_PMU_HW_CACHE_L1D 0
115 #define SBI_PMU_HW_CACHE_L1I 1
116 #define SBI_PMU_HW_CACHE_LL 2
117 #define SBI_PMU_HW_CACHE_DTLB 3
118 #define SBI_PMU_HW_CACHE_ITLB 4
119 #define SBI_PMU_HW_CACHE_BPU 5
120 #define SBI_PMU_HW_CACHE_NODE 6
121 #define SBI_PMU_HW_CACHE_MAX 7
122 
123 #define SBI_PMU_HW_CACHE_OP_READ 0
124 #define SBI_PMU_HW_CACHE_OP_WRITE 1
125 #define SBI_PMU_HW_CACHE_OP_PREFETCH 2
126 #define SBI_PMU_HW_CACHE_OP_MAX 3
127 
128 #define SBI_PMU_HW_CACHE_RESULT_ACCESS 0
129 #define SBI_PMU_HW_CACHE_RESULT_MISS 1
130 #define SBI_PMU_HW_CACHE_RESULT_MAX 2
131 
137 #define SBI_PMU_FW_MISALIGNED_LOAD 0
138 #define SBI_PMU_FW_MISALIGNED_STORE 1
139 #define SBI_PMU_FW_ACCESS_LOAD 2
140 #define SBI_PMU_FW_ACCESS_STORE 3
141 #define SBI_PMU_FW_ILLEGAL_INSN 4
142 #define SBI_PMU_FW_SET_TIMER 5
143 #define SBI_PMU_FW_IPI_SENT 6
144 #define SBI_PMU_FW_IPI_RECVD 7
145 #define SBI_PMU_FW_FENCE_I_SENT 8
146 #define SBI_PMU_FW_FENCE_I_RECVD 9
147 #define SBI_PMU_FW_SFENCE_VMA_SENT 10
148 #define SBI_PMU_FW_SFENCE_VMA_RCVD 11
149 #define SBI_PMU_FW_SFENCE_VMA_ASID_SENT 12
150 #define SBI_PMU_FW_SFENCE_VMA_ASID_RCVD 13
151 
152 #define SBI_PMU_FW_HFENCE_GVMA_SENT 14
153 #define SBI_PMU_FW_HFENCE_GVMA_RCVD 15
154 #define SBI_PMU_FW_HFENCE_GVMA_VMID_SENT 16
155 #define SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD 17
156 
157 #define SBI_PMU_FW_HFENCE_VVMA_SENT 18
158 #define SBI_PMU_FW_HFENCE_VVMA_RCVD 19
159 #define SBI_PMU_FW_HFENCE_VVMA_ASID_SENT 20
160 #define SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD 21
161 #define SBI_PMU_FW_MAX 22
162 /*
163  * Event codes 22 to 255 are reserved for future use.
164  * Event codes 256 to 65534 are reserved for SBI implementation
165  * specific custom firmware events.
166  */
167 #define SBI_PMU_FW_RESERVED_MAX 0xFFFE
168 /*
169  * Event code 0xFFFF is used for platform specific firmware
170  * events where the event data contains any event specific information.
171  */
172 #define SBI_PMU_FW_PLATFORM 0xFFFF
173 
175 #define SBI_PMU_EVENT_TYPE_HW 0x0
176 #define SBI_PMU_EVENT_TYPE_HW_CACHE 0x1
177 #define SBI_PMU_EVENT_TYPE_HW_RAW 0x2
178 #define SBI_PMU_EVENT_TYPE_FW 0xf
179 #define SBI_PMU_EVENT_TYPE_MAX 0x10
180 
182 #define SBI_PMU_CTR_TYPE_HW 0
183 #define SBI_PMU_CTR_TYPE_FW 1
184 
185 /* Helper macros to decode event idx */
186 #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
187 #define SBI_PMU_EVENT_IDX_TYPE_OFFSET 16
188 #define SBI_PMU_EVENT_IDX_TYPE_MASK (0xF << SBI_PMU_EVENT_IDX_TYPE_OFFSET)
189 #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
190 #define SBI_PMU_EVENT_RAW_IDX 0x20000
191 
192 #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
193 
194 #define SBI_PMU_EVENT_HW_CACHE_OPS_RESULT 0x1
195 #define SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK 0x6
196 #define SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET 1
197 #define SBI_PMU_EVENT_HW_CACHE_ID_MASK 0xfff8
198 #define SBI_PMU_EVENT_HW_CACHE_ID_OFFSET 3
199 
200 /* Flags defined for config matching function */
201 #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0)
202 #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1)
203 #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2)
204 #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3)
205 #define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4)
206 #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5)
207 #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6)
208 #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7)
209 
210 /* Flags defined for counter start function */
211 #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
212 
213 /* Flags defined for counter stop function */
214 #define SBI_PMU_STOP_FLAG_RESET (1 << 0)
215 
216 /* SBI function IDs for DBCN extension */
217 #define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
218 #define SBI_EXT_DBCN_CONSOLE_READ 0x1
219 #define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
220 
221 /* SBI function IDs for SUSP extension */
222 #define SBI_EXT_SUSP_SUSPEND 0x0
223 
224 #define SBI_SUSP_SLEEP_TYPE_SUSPEND 0x0
225 #define SBI_SUSP_SLEEP_TYPE_LAST SBI_SUSP_SLEEP_TYPE_SUSPEND
226 #define SBI_SUSP_PLATFORM_SLEEP_START 0x80000000
227 
228 /* SBI function IDs for CPPC extension */
229 #define SBI_EXT_CPPC_PROBE 0x0
230 #define SBI_EXT_CPPC_READ 0x1
231 #define SBI_EXT_CPPC_READ_HI 0x2
232 #define SBI_EXT_CPPC_WRITE 0x3
233 
234 #define SBI_CPPC_HIGHEST_PERF 0x00000000
235 #define SBI_CPPC_NOMINAL_PERF 0x00000001
236 #define SBI_CPPC_LOW_NON_LINEAR_PERF 0x00000002
237 #define SBI_CPPC_LOWEST_PERF 0x00000003
238 #define SBI_CPPC_GUARANTEED_PERF 0x00000004
239 #define SBI_CPPC_DESIRED_PERF 0x00000005
240 #define SBI_CPPC_MIN_PERF 0x00000006
241 #define SBI_CPPC_MAX_PERF 0x00000007
242 #define SBI_CPPC_PERF_REDUC_TOLERANCE 0x00000008
243 #define SBI_CPPC_TIME_WINDOW 0x00000009
244 #define SBI_CPPC_CTR_WRAP_TIME 0x0000000A
245 #define SBI_CPPC_REFERENCE_CTR 0x0000000B
246 #define SBI_CPPC_DELIVERED_CTR 0x0000000C
247 #define SBI_CPPC_PERF_LIMITED 0x0000000D
248 #define SBI_CPPC_ENABLE 0x0000000E
249 #define SBI_CPPC_AUTO_SEL_ENABLE 0x0000000F
250 #define SBI_CPPC_AUTO_ACT_WINDOW 0x00000010
251 #define SBI_CPPC_ENERGY_PERF_PREFERENCE 0x00000011
252 #define SBI_CPPC_REFERENCE_PERF 0x00000012
253 #define SBI_CPPC_LOWEST_FREQ 0x00000013
254 #define SBI_CPPC_NOMINAL_FREQ 0x00000014
255 #define SBI_CPPC_ACPI_LAST SBI_CPPC_NOMINAL_FREQ
256 #define SBI_CPPC_TRANSITION_LATENCY 0x80000000
257 #define SBI_CPPC_NON_ACPI_LAST SBI_CPPC_TRANSITION_LATENCY
258 
259 /* SBI base specification related macros */
260 #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
261 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
262 #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
263 #define SBI_EXT_VENDOR_START 0x09000000
264 #define SBI_EXT_VENDOR_END 0x09FFFFFF
265 #define SBI_EXT_FIRMWARE_START 0x0A000000
266 #define SBI_EXT_FIRMWARE_END 0x0AFFFFFF
267 
268 /* SBI return error codes */
269 #define SBI_SUCCESS 0
270 #define SBI_ERR_FAILED -1
271 #define SBI_ERR_NOT_SUPPORTED -2
272 #define SBI_ERR_INVALID_PARAM -3
273 #define SBI_ERR_DENIED -4
274 #define SBI_ERR_INVALID_ADDRESS -5
275 #define SBI_ERR_ALREADY_AVAILABLE -6
276 #define SBI_ERR_ALREADY_STARTED -7
277 #define SBI_ERR_ALREADY_STOPPED -8
278 
279 #define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED