6 static inline uint64_t asm_r_mhartid() {
8 asm volatile(
"csrr %0, mhartid" :
"=r"(x));
14 #define MSTATUS_MPP_MASK (3L << 11)
15 #define MSTATUS_MPP_M (3L << 11)
16 #define MSTATUS_MPP_S (1L << 11)
17 #define MSTATUS_MPP_U (0L << 11)
18 #define MSTATUS_MIE (1L << 3)
20 static inline uint64_t asm_r_mstatus() {
22 asm volatile(
"csrr %0, mstatus" :
"=r"(x));
26 static inline void asm_w_mstatus(uint64_t x) {
27 asm volatile(
"csrw mstatus, %0" : :
"r"(x));
33 static inline void asm_w_mepc(uint64_t x) {
34 asm volatile(
"csrw mepc, %0" : :
"r"(x));
39 #define SSTATUS_SPP (1L << 8)
40 #define SSTATUS_SPIE (1L << 5)
41 #define SSTATUS_UPIE (1L << 4)
42 #define SSTATUS_SIE (1L << 1)
43 #define SSTATUS_UIE (1L << 0)
45 static inline uint64_t asm_r_sstatus() {
47 asm volatile(
"csrr %0, sstatus" :
"=r"(x));
51 static inline void asm_w_sstatus(uint64_t x) {
52 asm volatile(
"csrw sstatus, %0" : :
"r"(x));
56 static inline uint64_t asm_r_sip() {
58 asm volatile(
"csrr %0, sip" :
"=r"(x));
62 static inline void asm_w_sip(uint64_t x) {
63 asm volatile(
"csrw sip, %0" : :
"r"(x));
67 #define SIE_SEIE (1L << 9)
68 #define SIE_STIE (1L << 5)
69 #define SIE_SSIE (1L << 1)
70 static inline uint64_t asm_r_sie() {
72 asm volatile(
"csrr %0, sie" :
"=r"(x));
76 static inline void asm_w_sie(uint64_t x) {
77 asm volatile(
"csrw sie, %0" : :
"r"(x));
81 #define MIE_MEIE (1L << 11)
82 #define MIE_MTIE (1L << 7)
83 #define MIE_MSIE (1L << 3)
84 static inline uint64_t asm_r_mie() {
86 asm volatile(
"csrr %0, mie" :
"=r"(x));
90 static inline void asm_w_mie(uint64_t x) {
91 asm volatile(
"csrw mie, %0" : :
"r"(x));
97 static inline void asm_w_sepc(uint64_t x) {
98 asm volatile(
"csrw sepc, %0" : :
"r"(x));
101 static inline uint64_t asm_r_sepc() {
103 asm volatile(
"csrr %0, sepc" :
"=r"(x));
108 static inline uint64_t asm_r_medeleg() {
110 asm volatile(
"csrr %0, medeleg" :
"=r"(x));
114 static inline void asm_w_medeleg(uint64_t x) {
115 asm volatile(
"csrw medeleg, %0" : :
"r"(x));
119 static inline uint64_t asm_r_mideleg() {
121 asm volatile(
"csrr %0, mideleg" :
"=r"(x));
125 static inline void asm_w_mideleg(uint64_t x) {
126 asm volatile(
"csrw mideleg, %0" : :
"r"(x));
131 static inline void asm_w_stvec(uint64_t x) {
132 asm volatile(
"csrw stvec, %0" : :
"r"(x));
135 static inline uint64_t asm_r_stvec() {
137 asm volatile(
"csrr %0, stvec" :
"=r"(x));
142 static inline void asm_w_mtvec(uint64_t x) {
143 asm volatile(
"csrw mtvec, %0" : :
"r"(x));
147 #define SATP_SV39 (8L << 60)
149 #define MAKE_SATP(pagetable) (SATP_SV39 | (((uint64_t)pagetable) >> 12))
153 static inline void asm_w_satp(uint64_t x) {
154 asm volatile(
"csrw satp, %0" : :
"r"(x));
157 static inline uint64_t asm_r_satp() {
159 asm volatile(
"csrr %0, satp" :
"=r"(x));
164 static inline void asm_w_sscratch(uint64_t x) {
165 asm volatile(
"csrw sscratch, %0" : :
"r"(x));
168 static inline void asm_w_mscratch(uint64_t x) {
169 asm volatile(
"csrw mscratch, %0" : :
"r"(x));
173 static inline uint64_t asm_r_scause() {
175 asm volatile(
"csrr %0, scause" :
"=r"(x));
180 static inline uint64_t asm_r_stval() {
182 asm volatile(
"csrr %0, stval" :
"=r"(x));
187 static inline void asm_w_mcounteren(uint64_t x) {
188 asm volatile(
"csrw mcounteren, %0" : :
"r"(x));
191 static inline uint64_t asm_r_mcounteren() {
193 asm volatile(
"csrr %0, mcounteren" :
"=r"(x));
198 static inline uint64_t asm_r_time() {
202 asm volatile(
"rdtime %0" :
"=r"(x));
207 static inline void intr_on() {
212 static inline void intr_off() {
217 static inline int intr_get() {
218 uint64_t x = asm_r_sstatus();
222 static inline uint64_t asm_r_sp() {
224 asm volatile(
"mv %0, sp" :
"=r"(x));
230 static inline uint64_t asm_r_tp() {
232 asm volatile(
"mv %0, tp" :
"=r"(x));
236 static inline void asm_w_tp(uint64_t x) {
237 asm volatile(
"mv tp, %0" : :
"r"(x));
240 static inline uint64_t asm_r_ra() {
242 asm volatile(
"mv %0, ra" :
"=r"(x));
247 static inline void sfence_vma() {
250 asm volatile(
"sfence.vma");
#define SSTATUS_SIE
Definition: privileged.h:42