550W Document
550W, a high-end OS
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宏定义 | |
#define | SAVE(x, y) sd x, OFFSET_REG_##y##(sp) |
#define | LOAD(x, y) ld x, OFFSET_REG_##y##(sp) |
#define | reg_ra 0 |
#define | reg_sp 1 |
#define | reg_gp 2 |
#define | reg_tp 3 |
#define | reg_t0 4 |
#define | reg_t1 5 |
#define | reg_t2 6 |
#define | reg_s0 7 |
#define | reg_s1 8 |
#define | reg_a0 9 |
#define | reg_a1 10 |
#define | reg_a2 11 |
#define | reg_a3 12 |
#define | reg_a4 13 |
#define | reg_a5 14 |
#define | reg_a6 15 |
#define | reg_a7 16 |
#define | reg_s2 17 |
#define | reg_s3 18 |
#define | reg_s4 19 |
#define | reg_s5 20 |
#define | reg_s6 21 |
#define | reg_s7 22 |
#define | reg_s8 23 |
#define | reg_s9 24 |
#define | reg_s10 25 |
#define | reg_s11 26 |
#define | reg_t3 27 |
#define | reg_t4 28 |
#define | reg_t5 29 |
#define | reg_t6 30 |
#define | reg_sstatus 31 |
#define | reg_sepc 32 |
#define | reg_sbadaddr 33 |
#define | reg_scause 34 |
#define | OFFSET_REG_RA 0 |
#define | OFFSET_REG_SP 8 |
#define | OFFSET_REG_GP 16 |
#define | OFFSET_REG_TP 24 |
#define | OFFSET_REG_T0 32 |
#define | OFFSET_REG_T1 40 |
#define | OFFSET_REG_T2 48 |
#define | OFFSET_REG_S0 56 |
#define | OFFSET_REG_S1 64 |
#define | OFFSET_REG_A0 72 |
#define | OFFSET_REG_A1 80 |
#define | OFFSET_REG_A2 88 |
#define | OFFSET_REG_A3 96 |
#define | OFFSET_REG_A4 104 |
#define | OFFSET_REG_A5 112 |
#define | OFFSET_REG_A6 120 |
#define | OFFSET_REG_A7 128 |
#define | OFFSET_REG_S2 136 |
#define | OFFSET_REG_S3 144 |
#define | OFFSET_REG_S4 152 |
#define | OFFSET_REG_S5 160 |
#define | OFFSET_REG_S6 168 |
#define | OFFSET_REG_S7 176 |
#define | OFFSET_REG_S8 184 |
#define | OFFSET_REG_S9 192 |
#define | OFFSET_REG_S10 200 |
#define | OFFSET_REG_S11 208 |
#define | OFFSET_REG_T3 216 |
#define | OFFSET_REG_T4 224 |
#define | OFFSET_REG_T5 232 |
#define | OFFSET_REG_T6 240 |
#define | OFFSET_REG_SIZE 248 |
#define | OFFSET_REG_SSTATUS 248 |
#define | OFFSET_REG_SEPC 256 |
#define | OFFSET_REG_SBADADDR 264 |
#define | OFFSET_REG_SCAUSE 272 |
#define | OFFSET_ALL_REG_SIZE 280 |
#define | PCB_KERNEL_SP 0 |
#define | PCB_USER_SP 8 |
#define | switch_reg_ra 0 |
#define | switch_reg_sp 1 |
#define | switch_reg_s0 2 |
#define | switch_reg_s1 3 |
#define | switch_reg_s2 4 |
#define | switch_reg_s3 5 |
#define | switch_reg_s4 6 |
#define | switch_reg_s5 7 |
#define | switch_reg_s6 8 |
#define | switch_reg_s7 9 |
#define | switch_reg_s8 10 |
#define | switch_reg_s9 11 |
#define | switch_reg_s10 12 |
#define | switch_reg_s11 13 |
#define | SS(x, y) sd x, SWITCH_TO_##y##(t0) |
#define | LS(x, y) ld x, SWITCH_TO_##y##(t0) |
#define | SWITCH_TO_RA 0 |
#define | SWITCH_TO_SP 8 |
#define | SWITCH_TO_S0 16 |
#define | SWITCH_TO_S1 24 |
#define | SWITCH_TO_S2 32 |
#define | SWITCH_TO_S3 40 |
#define | SWITCH_TO_S4 48 |
#define | SWITCH_TO_S5 56 |
#define | SWITCH_TO_S6 64 |
#define | SWITCH_TO_S7 72 |
#define | SWITCH_TO_S8 80 |
#define | SWITCH_TO_S9 88 |
#define | SWITCH_TO_S10 96 |
#define | SWITCH_TO_S11 104 |
#define | SWITCH_TO_SIZE 112 |
#define LOAD | ( | x, | |
y | |||
) | ld x, OFFSET_REG_##y##(sp) |
#define LS | ( | x, | |
y | |||
) | ld x, SWITCH_TO_##y##(t0) |
#define OFFSET_ALL_REG_SIZE 280 |
#define OFFSET_REG_A0 72 |
#define OFFSET_REG_A1 80 |
#define OFFSET_REG_A2 88 |
#define OFFSET_REG_A3 96 |
#define OFFSET_REG_A4 104 |
#define OFFSET_REG_A5 112 |
#define OFFSET_REG_A6 120 |
#define OFFSET_REG_A7 128 |
#define OFFSET_REG_GP 16 |
#define OFFSET_REG_RA 0 |
#define OFFSET_REG_S0 56 |
#define OFFSET_REG_S1 64 |
#define OFFSET_REG_S10 200 |
#define OFFSET_REG_S11 208 |
#define OFFSET_REG_S2 136 |
#define OFFSET_REG_S3 144 |
#define OFFSET_REG_S4 152 |
#define OFFSET_REG_S5 160 |
#define OFFSET_REG_S6 168 |
#define OFFSET_REG_S7 176 |
#define OFFSET_REG_S8 184 |
#define OFFSET_REG_S9 192 |
#define OFFSET_REG_SBADADDR 264 |
#define OFFSET_REG_SCAUSE 272 |
#define OFFSET_REG_SEPC 256 |
#define OFFSET_REG_SIZE 248 |
#define OFFSET_REG_SP 8 |
#define OFFSET_REG_SSTATUS 248 |
#define OFFSET_REG_T0 32 |
#define OFFSET_REG_T1 40 |
#define OFFSET_REG_T2 48 |
#define OFFSET_REG_T3 216 |
#define OFFSET_REG_T4 224 |
#define OFFSET_REG_T5 232 |
#define OFFSET_REG_T6 240 |
#define OFFSET_REG_TP 24 |
#define PCB_KERNEL_SP 0 |
#define PCB_USER_SP 8 |
#define reg_a0 9 |
#define reg_a1 10 |
#define reg_a2 11 |
#define reg_a3 12 |
#define reg_a4 13 |
#define reg_a5 14 |
#define reg_a6 15 |
#define reg_a7 16 |
#define reg_gp 2 |
#define reg_ra 0 |
#define reg_s0 7 |
#define reg_s1 8 |
#define reg_s10 25 |
#define reg_s11 26 |
#define reg_s2 17 |
#define reg_s3 18 |
#define reg_s4 19 |
#define reg_s5 20 |
#define reg_s6 21 |
#define reg_s7 22 |
#define reg_s8 23 |
#define reg_s9 24 |
#define reg_sbadaddr 33 |
#define reg_scause 34 |
#define reg_sepc 32 |
#define reg_sp 1 |
#define reg_sstatus 31 |
#define reg_t0 4 |
#define reg_t1 5 |
#define reg_t2 6 |
#define reg_t3 27 |
#define reg_t4 28 |
#define reg_t5 29 |
#define reg_t6 30 |
#define reg_tp 3 |
#define SAVE | ( | x, | |
y | |||
) | sd x, OFFSET_REG_##y##(sp) |
#define SS | ( | x, | |
y | |||
) | sd x, SWITCH_TO_##y##(t0) |
#define switch_reg_ra 0 |
#define switch_reg_s0 2 |
#define switch_reg_s1 3 |
#define switch_reg_s10 12 |
#define switch_reg_s11 13 |
#define switch_reg_s2 4 |
#define switch_reg_s3 5 |
#define switch_reg_s4 6 |
#define switch_reg_s5 7 |
#define switch_reg_s6 8 |
#define switch_reg_s7 9 |
#define switch_reg_s8 10 |
#define switch_reg_s9 11 |
#define switch_reg_sp 1 |
#define SWITCH_TO_RA 0 |
#define SWITCH_TO_S0 16 |
#define SWITCH_TO_S1 24 |
#define SWITCH_TO_S10 96 |
#define SWITCH_TO_S11 104 |
#define SWITCH_TO_S2 32 |
#define SWITCH_TO_S3 40 |
#define SWITCH_TO_S4 48 |
#define SWITCH_TO_S5 56 |
#define SWITCH_TO_S6 64 |
#define SWITCH_TO_S7 72 |
#define SWITCH_TO_S8 80 |
#define SWITCH_TO_S9 88 |
#define SWITCH_TO_SIZE 112 |
#define SWITCH_TO_SP 8 |