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sbidef.h 文件参考
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浏览源代码.

宏定义

#define SBI_EXT_0_1_SET_TIMER   0x0
 
#define SBI_EXT_0_1_CONSOLE_PUTCHAR   0x1
 
#define SBI_EXT_0_1_CONSOLE_GETCHAR   0x2
 
#define SBI_EXT_0_1_CLEAR_IPI   0x3
 
#define SBI_EXT_0_1_SEND_IPI   0x4
 
#define SBI_EXT_0_1_REMOTE_FENCE_I   0x5
 
#define SBI_EXT_0_1_REMOTE_SFENCE_VMA   0x6
 
#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID   0x7
 
#define SBI_EXT_0_1_SHUTDOWN   0x8
 
#define SBI_EXT_BASE   0x10
 
#define SBI_EXT_TIME   0x54494D45
 
#define SBI_EXT_IPI   0x735049
 
#define SBI_EXT_RFENCE   0x52464E43
 
#define SBI_EXT_HSM   0x48534D
 
#define SBI_EXT_SRST   0x53525354
 
#define SBI_EXT_PMU   0x504D55
 
#define SBI_EXT_DBCN   0x4442434E
 
#define SBI_EXT_SUSP   0x53555350
 
#define SBI_EXT_CPPC   0x43505043
 
#define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
 
#define SBI_EXT_BASE_GET_IMP_ID   0x1
 
#define SBI_EXT_BASE_GET_IMP_VERSION   0x2
 
#define SBI_EXT_BASE_PROBE_EXT   0x3
 
#define SBI_EXT_BASE_GET_MVENDORID   0x4
 
#define SBI_EXT_BASE_GET_MARCHID   0x5
 
#define SBI_EXT_BASE_GET_MIMPID   0x6
 
#define SBI_EXT_TIME_SET_TIMER   0x0
 
#define SBI_EXT_IPI_SEND_IPI   0x0
 
#define SBI_EXT_RFENCE_REMOTE_FENCE_I   0x0
 
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA   0x1
 
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID   0x2
 
#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID   0x3
 
#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA   0x4
 
#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID   0x5
 
#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA   0x6
 
#define SBI_EXT_HSM_HART_START   0x0
 
#define SBI_EXT_HSM_HART_STOP   0x1
 
#define SBI_EXT_HSM_HART_GET_STATUS   0x2
 
#define SBI_EXT_HSM_HART_SUSPEND   0x3
 
#define SBI_HSM_STATE_STARTED   0x0
 
#define SBI_HSM_STATE_STOPPED   0x1
 
#define SBI_HSM_STATE_START_PENDING   0x2
 
#define SBI_HSM_STATE_STOP_PENDING   0x3
 
#define SBI_HSM_STATE_SUSPENDED   0x4
 
#define SBI_HSM_STATE_SUSPEND_PENDING   0x5
 
#define SBI_HSM_STATE_RESUME_PENDING   0x6
 
#define SBI_HSM_SUSP_BASE_MASK   0x7fffffff
 
#define SBI_HSM_SUSP_NON_RET_BIT   0x80000000
 
#define SBI_HSM_SUSP_PLAT_BASE   0x10000000
 
#define SBI_HSM_SUSPEND_RET_DEFAULT   0x00000000
 
#define SBI_HSM_SUSPEND_RET_PLATFORM   SBI_HSM_SUSP_PLAT_BASE
 
#define SBI_HSM_SUSPEND_RET_LAST   SBI_HSM_SUSP_BASE_MASK
 
#define SBI_HSM_SUSPEND_NON_RET_DEFAULT   SBI_HSM_SUSP_NON_RET_BIT
 
#define SBI_HSM_SUSPEND_NON_RET_PLATFORM   (SBI_HSM_SUSP_NON_RET_BIT | SBI_HSM_SUSP_PLAT_BASE)
 
#define SBI_HSM_SUSPEND_NON_RET_LAST   (SBI_HSM_SUSP_NON_RET_BIT | SBI_HSM_SUSP_BASE_MASK)
 
#define SBI_EXT_SRST_RESET   0x0
 
#define SBI_SRST_RESET_TYPE_SHUTDOWN   0x0
 
#define SBI_SRST_RESET_TYPE_COLD_REBOOT   0x1
 
#define SBI_SRST_RESET_TYPE_WARM_REBOOT   0x2
 
#define SBI_SRST_RESET_TYPE_LAST   SBI_SRST_RESET_TYPE_WARM_REBOOT
 
#define SBI_SRST_RESET_REASON_NONE   0x0
 
#define SBI_SRST_RESET_REASON_SYSFAIL   0x1
 
#define SBI_EXT_PMU_NUM_COUNTERS   0x0
 
#define SBI_EXT_PMU_COUNTER_GET_INFO   0x1
 
#define SBI_EXT_PMU_COUNTER_CFG_MATCH   0x2
 
#define SBI_EXT_PMU_COUNTER_START   0x3
 
#define SBI_EXT_PMU_COUNTER_STOP   0x4
 
#define SBI_EXT_PMU_COUNTER_FW_READ   0x5
 
#define SBI_EXT_PMU_COUNTER_FW_READ_HI   0x6
 
#define SBI_PMU_HW_NO_EVENT   0
 
#define SBI_PMU_HW_CPU_CYCLES   1
 
#define SBI_PMU_HW_INSTRUCTIONS   2
 
#define SBI_PMU_HW_CACHE_REFERENCES   3
 
#define SBI_PMU_HW_CACHE_MISSES   4
 
#define SBI_PMU_HW_BRANCH_INSTRUCTIONS   5
 
#define SBI_PMU_HW_BRANCH_MISSES   6
 
#define SBI_PMU_HW_BUS_CYCLES   7
 
#define SBI_PMU_HW_STALLED_CYCLES_FRONTEND   8
 
#define SBI_PMU_HW_STALLED_CYCLES_BACKEND   9
 
#define SBI_PMU_HW_REF_CPU_CYCLES   10
 
#define SBI_PMU_HW_GENERAL_MAX   11
 
#define SBI_PMU_HW_CACHE_L1D   0
 
#define SBI_PMU_HW_CACHE_L1I   1
 
#define SBI_PMU_HW_CACHE_LL   2
 
#define SBI_PMU_HW_CACHE_DTLB   3
 
#define SBI_PMU_HW_CACHE_ITLB   4
 
#define SBI_PMU_HW_CACHE_BPU   5
 
#define SBI_PMU_HW_CACHE_NODE   6
 
#define SBI_PMU_HW_CACHE_MAX   7
 
#define SBI_PMU_HW_CACHE_OP_READ   0
 
#define SBI_PMU_HW_CACHE_OP_WRITE   1
 
#define SBI_PMU_HW_CACHE_OP_PREFETCH   2
 
#define SBI_PMU_HW_CACHE_OP_MAX   3
 
#define SBI_PMU_HW_CACHE_RESULT_ACCESS   0
 
#define SBI_PMU_HW_CACHE_RESULT_MISS   1
 
#define SBI_PMU_HW_CACHE_RESULT_MAX   2
 
#define SBI_PMU_FW_MISALIGNED_LOAD   0
 
#define SBI_PMU_FW_MISALIGNED_STORE   1
 
#define SBI_PMU_FW_ACCESS_LOAD   2
 
#define SBI_PMU_FW_ACCESS_STORE   3
 
#define SBI_PMU_FW_ILLEGAL_INSN   4
 
#define SBI_PMU_FW_SET_TIMER   5
 
#define SBI_PMU_FW_IPI_SENT   6
 
#define SBI_PMU_FW_IPI_RECVD   7
 
#define SBI_PMU_FW_FENCE_I_SENT   8
 
#define SBI_PMU_FW_FENCE_I_RECVD   9
 
#define SBI_PMU_FW_SFENCE_VMA_SENT   10
 
#define SBI_PMU_FW_SFENCE_VMA_RCVD   11
 
#define SBI_PMU_FW_SFENCE_VMA_ASID_SENT   12
 
#define SBI_PMU_FW_SFENCE_VMA_ASID_RCVD   13
 
#define SBI_PMU_FW_HFENCE_GVMA_SENT   14
 
#define SBI_PMU_FW_HFENCE_GVMA_RCVD   15
 
#define SBI_PMU_FW_HFENCE_GVMA_VMID_SENT   16
 
#define SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD   17
 
#define SBI_PMU_FW_HFENCE_VVMA_SENT   18
 
#define SBI_PMU_FW_HFENCE_VVMA_RCVD   19
 
#define SBI_PMU_FW_HFENCE_VVMA_ASID_SENT   20
 
#define SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD   21
 
#define SBI_PMU_FW_MAX   22
 
#define SBI_PMU_FW_RESERVED_MAX   0xFFFE
 
#define SBI_PMU_FW_PLATFORM   0xFFFF
 
#define SBI_PMU_EVENT_TYPE_HW   0x0
 
#define SBI_PMU_EVENT_TYPE_HW_CACHE   0x1
 
#define SBI_PMU_EVENT_TYPE_HW_RAW   0x2
 
#define SBI_PMU_EVENT_TYPE_FW   0xf
 
#define SBI_PMU_EVENT_TYPE_MAX   0x10
 
#define SBI_PMU_CTR_TYPE_HW   0
 
#define SBI_PMU_CTR_TYPE_FW   1
 
#define SBI_PMU_EVENT_IDX_MASK   0xFFFFF
 
#define SBI_PMU_EVENT_IDX_TYPE_OFFSET   16
 
#define SBI_PMU_EVENT_IDX_TYPE_MASK   (0xF << SBI_PMU_EVENT_IDX_TYPE_OFFSET)
 
#define SBI_PMU_EVENT_IDX_CODE_MASK   0xFFFF
 
#define SBI_PMU_EVENT_RAW_IDX   0x20000
 
#define SBI_PMU_EVENT_IDX_INVALID   0xFFFFFFFF
 
#define SBI_PMU_EVENT_HW_CACHE_OPS_RESULT   0x1
 
#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK   0x6
 
#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET   1
 
#define SBI_PMU_EVENT_HW_CACHE_ID_MASK   0xfff8
 
#define SBI_PMU_EVENT_HW_CACHE_ID_OFFSET   3
 
#define SBI_PMU_CFG_FLAG_SKIP_MATCH   (1 << 0)
 
#define SBI_PMU_CFG_FLAG_CLEAR_VALUE   (1 << 1)
 
#define SBI_PMU_CFG_FLAG_AUTO_START   (1 << 2)
 
#define SBI_PMU_CFG_FLAG_SET_VUINH   (1 << 3)
 
#define SBI_PMU_CFG_FLAG_SET_VSINH   (1 << 4)
 
#define SBI_PMU_CFG_FLAG_SET_UINH   (1 << 5)
 
#define SBI_PMU_CFG_FLAG_SET_SINH   (1 << 6)
 
#define SBI_PMU_CFG_FLAG_SET_MINH   (1 << 7)
 
#define SBI_PMU_START_FLAG_SET_INIT_VALUE   (1 << 0)
 
#define SBI_PMU_STOP_FLAG_RESET   (1 << 0)
 
#define SBI_EXT_DBCN_CONSOLE_WRITE   0x0
 
#define SBI_EXT_DBCN_CONSOLE_READ   0x1
 
#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE   0x2
 
#define SBI_EXT_SUSP_SUSPEND   0x0
 
#define SBI_SUSP_SLEEP_TYPE_SUSPEND   0x0
 
#define SBI_SUSP_SLEEP_TYPE_LAST   SBI_SUSP_SLEEP_TYPE_SUSPEND
 
#define SBI_SUSP_PLATFORM_SLEEP_START   0x80000000
 
#define SBI_EXT_CPPC_PROBE   0x0
 
#define SBI_EXT_CPPC_READ   0x1
 
#define SBI_EXT_CPPC_READ_HI   0x2
 
#define SBI_EXT_CPPC_WRITE   0x3
 
#define SBI_CPPC_HIGHEST_PERF   0x00000000
 
#define SBI_CPPC_NOMINAL_PERF   0x00000001
 
#define SBI_CPPC_LOW_NON_LINEAR_PERF   0x00000002
 
#define SBI_CPPC_LOWEST_PERF   0x00000003
 
#define SBI_CPPC_GUARANTEED_PERF   0x00000004
 
#define SBI_CPPC_DESIRED_PERF   0x00000005
 
#define SBI_CPPC_MIN_PERF   0x00000006
 
#define SBI_CPPC_MAX_PERF   0x00000007
 
#define SBI_CPPC_PERF_REDUC_TOLERANCE   0x00000008
 
#define SBI_CPPC_TIME_WINDOW   0x00000009
 
#define SBI_CPPC_CTR_WRAP_TIME   0x0000000A
 
#define SBI_CPPC_REFERENCE_CTR   0x0000000B
 
#define SBI_CPPC_DELIVERED_CTR   0x0000000C
 
#define SBI_CPPC_PERF_LIMITED   0x0000000D
 
#define SBI_CPPC_ENABLE   0x0000000E
 
#define SBI_CPPC_AUTO_SEL_ENABLE   0x0000000F
 
#define SBI_CPPC_AUTO_ACT_WINDOW   0x00000010
 
#define SBI_CPPC_ENERGY_PERF_PREFERENCE   0x00000011
 
#define SBI_CPPC_REFERENCE_PERF   0x00000012
 
#define SBI_CPPC_LOWEST_FREQ   0x00000013
 
#define SBI_CPPC_NOMINAL_FREQ   0x00000014
 
#define SBI_CPPC_ACPI_LAST   SBI_CPPC_NOMINAL_FREQ
 
#define SBI_CPPC_TRANSITION_LATENCY   0x80000000
 
#define SBI_CPPC_NON_ACPI_LAST   SBI_CPPC_TRANSITION_LATENCY
 
#define SBI_SPEC_VERSION_MAJOR_OFFSET   24
 
#define SBI_SPEC_VERSION_MAJOR_MASK   0x7f
 
#define SBI_SPEC_VERSION_MINOR_MASK   0xffffff
 
#define SBI_EXT_VENDOR_START   0x09000000
 
#define SBI_EXT_VENDOR_END   0x09FFFFFF
 
#define SBI_EXT_FIRMWARE_START   0x0A000000
 
#define SBI_EXT_FIRMWARE_END   0x0AFFFFFF
 
#define SBI_SUCCESS   0
 
#define SBI_ERR_FAILED   -1
 
#define SBI_ERR_NOT_SUPPORTED   -2
 
#define SBI_ERR_INVALID_PARAM   -3
 
#define SBI_ERR_DENIED   -4
 
#define SBI_ERR_INVALID_ADDRESS   -5
 
#define SBI_ERR_ALREADY_AVAILABLE   -6
 
#define SBI_ERR_ALREADY_STARTED   -7
 
#define SBI_ERR_ALREADY_STOPPED   -8
 

宏定义说明

◆ SBI_CPPC_ACPI_LAST

#define SBI_CPPC_ACPI_LAST   SBI_CPPC_NOMINAL_FREQ

◆ SBI_CPPC_AUTO_ACT_WINDOW

#define SBI_CPPC_AUTO_ACT_WINDOW   0x00000010

◆ SBI_CPPC_AUTO_SEL_ENABLE

#define SBI_CPPC_AUTO_SEL_ENABLE   0x0000000F

◆ SBI_CPPC_CTR_WRAP_TIME

#define SBI_CPPC_CTR_WRAP_TIME   0x0000000A

◆ SBI_CPPC_DELIVERED_CTR

#define SBI_CPPC_DELIVERED_CTR   0x0000000C

◆ SBI_CPPC_DESIRED_PERF

#define SBI_CPPC_DESIRED_PERF   0x00000005

◆ SBI_CPPC_ENABLE

#define SBI_CPPC_ENABLE   0x0000000E

◆ SBI_CPPC_ENERGY_PERF_PREFERENCE

#define SBI_CPPC_ENERGY_PERF_PREFERENCE   0x00000011

◆ SBI_CPPC_GUARANTEED_PERF

#define SBI_CPPC_GUARANTEED_PERF   0x00000004

◆ SBI_CPPC_HIGHEST_PERF

#define SBI_CPPC_HIGHEST_PERF   0x00000000

◆ SBI_CPPC_LOW_NON_LINEAR_PERF

#define SBI_CPPC_LOW_NON_LINEAR_PERF   0x00000002

◆ SBI_CPPC_LOWEST_FREQ

#define SBI_CPPC_LOWEST_FREQ   0x00000013

◆ SBI_CPPC_LOWEST_PERF

#define SBI_CPPC_LOWEST_PERF   0x00000003

◆ SBI_CPPC_MAX_PERF

#define SBI_CPPC_MAX_PERF   0x00000007

◆ SBI_CPPC_MIN_PERF

#define SBI_CPPC_MIN_PERF   0x00000006

◆ SBI_CPPC_NOMINAL_FREQ

#define SBI_CPPC_NOMINAL_FREQ   0x00000014

◆ SBI_CPPC_NOMINAL_PERF

#define SBI_CPPC_NOMINAL_PERF   0x00000001

◆ SBI_CPPC_NON_ACPI_LAST

#define SBI_CPPC_NON_ACPI_LAST   SBI_CPPC_TRANSITION_LATENCY

◆ SBI_CPPC_PERF_LIMITED

#define SBI_CPPC_PERF_LIMITED   0x0000000D

◆ SBI_CPPC_PERF_REDUC_TOLERANCE

#define SBI_CPPC_PERF_REDUC_TOLERANCE   0x00000008

◆ SBI_CPPC_REFERENCE_CTR

#define SBI_CPPC_REFERENCE_CTR   0x0000000B

◆ SBI_CPPC_REFERENCE_PERF

#define SBI_CPPC_REFERENCE_PERF   0x00000012

◆ SBI_CPPC_TIME_WINDOW

#define SBI_CPPC_TIME_WINDOW   0x00000009

◆ SBI_CPPC_TRANSITION_LATENCY

#define SBI_CPPC_TRANSITION_LATENCY   0x80000000

◆ SBI_ERR_ALREADY_AVAILABLE

#define SBI_ERR_ALREADY_AVAILABLE   -6

◆ SBI_ERR_ALREADY_STARTED

#define SBI_ERR_ALREADY_STARTED   -7

◆ SBI_ERR_ALREADY_STOPPED

#define SBI_ERR_ALREADY_STOPPED   -8

◆ SBI_ERR_DENIED

#define SBI_ERR_DENIED   -4

◆ SBI_ERR_FAILED

#define SBI_ERR_FAILED   -1

◆ SBI_ERR_INVALID_ADDRESS

#define SBI_ERR_INVALID_ADDRESS   -5

◆ SBI_ERR_INVALID_PARAM

#define SBI_ERR_INVALID_PARAM   -3

◆ SBI_ERR_NOT_SUPPORTED

#define SBI_ERR_NOT_SUPPORTED   -2

◆ SBI_EXT_0_1_CLEAR_IPI

#define SBI_EXT_0_1_CLEAR_IPI   0x3

◆ SBI_EXT_0_1_CONSOLE_GETCHAR

#define SBI_EXT_0_1_CONSOLE_GETCHAR   0x2

◆ SBI_EXT_0_1_CONSOLE_PUTCHAR

#define SBI_EXT_0_1_CONSOLE_PUTCHAR   0x1

◆ SBI_EXT_0_1_REMOTE_FENCE_I

#define SBI_EXT_0_1_REMOTE_FENCE_I   0x5

◆ SBI_EXT_0_1_REMOTE_SFENCE_VMA

#define SBI_EXT_0_1_REMOTE_SFENCE_VMA   0x6

◆ SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID

#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID   0x7

◆ SBI_EXT_0_1_SEND_IPI

#define SBI_EXT_0_1_SEND_IPI   0x4

◆ SBI_EXT_0_1_SET_TIMER

#define SBI_EXT_0_1_SET_TIMER   0x0

◆ SBI_EXT_0_1_SHUTDOWN

#define SBI_EXT_0_1_SHUTDOWN   0x8

◆ SBI_EXT_BASE

#define SBI_EXT_BASE   0x10

◆ SBI_EXT_BASE_GET_IMP_ID

#define SBI_EXT_BASE_GET_IMP_ID   0x1

◆ SBI_EXT_BASE_GET_IMP_VERSION

#define SBI_EXT_BASE_GET_IMP_VERSION   0x2

◆ SBI_EXT_BASE_GET_MARCHID

#define SBI_EXT_BASE_GET_MARCHID   0x5

◆ SBI_EXT_BASE_GET_MIMPID

#define SBI_EXT_BASE_GET_MIMPID   0x6

◆ SBI_EXT_BASE_GET_MVENDORID

#define SBI_EXT_BASE_GET_MVENDORID   0x4

◆ SBI_EXT_BASE_GET_SPEC_VERSION

#define SBI_EXT_BASE_GET_SPEC_VERSION   0x0

◆ SBI_EXT_BASE_PROBE_EXT

#define SBI_EXT_BASE_PROBE_EXT   0x3

◆ SBI_EXT_CPPC

#define SBI_EXT_CPPC   0x43505043

◆ SBI_EXT_CPPC_PROBE

#define SBI_EXT_CPPC_PROBE   0x0

◆ SBI_EXT_CPPC_READ

#define SBI_EXT_CPPC_READ   0x1

◆ SBI_EXT_CPPC_READ_HI

#define SBI_EXT_CPPC_READ_HI   0x2

◆ SBI_EXT_CPPC_WRITE

#define SBI_EXT_CPPC_WRITE   0x3

◆ SBI_EXT_DBCN

#define SBI_EXT_DBCN   0x4442434E

◆ SBI_EXT_DBCN_CONSOLE_READ

#define SBI_EXT_DBCN_CONSOLE_READ   0x1

◆ SBI_EXT_DBCN_CONSOLE_WRITE

#define SBI_EXT_DBCN_CONSOLE_WRITE   0x0

◆ SBI_EXT_DBCN_CONSOLE_WRITE_BYTE

#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE   0x2

◆ SBI_EXT_FIRMWARE_END

#define SBI_EXT_FIRMWARE_END   0x0AFFFFFF

◆ SBI_EXT_FIRMWARE_START

#define SBI_EXT_FIRMWARE_START   0x0A000000

◆ SBI_EXT_HSM

#define SBI_EXT_HSM   0x48534D

◆ SBI_EXT_HSM_HART_GET_STATUS

#define SBI_EXT_HSM_HART_GET_STATUS   0x2

◆ SBI_EXT_HSM_HART_START

#define SBI_EXT_HSM_HART_START   0x0

◆ SBI_EXT_HSM_HART_STOP

#define SBI_EXT_HSM_HART_STOP   0x1

◆ SBI_EXT_HSM_HART_SUSPEND

#define SBI_EXT_HSM_HART_SUSPEND   0x3

◆ SBI_EXT_IPI

#define SBI_EXT_IPI   0x735049

◆ SBI_EXT_IPI_SEND_IPI

#define SBI_EXT_IPI_SEND_IPI   0x0

◆ SBI_EXT_PMU

#define SBI_EXT_PMU   0x504D55

◆ SBI_EXT_PMU_COUNTER_CFG_MATCH

#define SBI_EXT_PMU_COUNTER_CFG_MATCH   0x2

◆ SBI_EXT_PMU_COUNTER_FW_READ

#define SBI_EXT_PMU_COUNTER_FW_READ   0x5

◆ SBI_EXT_PMU_COUNTER_FW_READ_HI

#define SBI_EXT_PMU_COUNTER_FW_READ_HI   0x6

◆ SBI_EXT_PMU_COUNTER_GET_INFO

#define SBI_EXT_PMU_COUNTER_GET_INFO   0x1

◆ SBI_EXT_PMU_COUNTER_START

#define SBI_EXT_PMU_COUNTER_START   0x3

◆ SBI_EXT_PMU_COUNTER_STOP

#define SBI_EXT_PMU_COUNTER_STOP   0x4

◆ SBI_EXT_PMU_NUM_COUNTERS

#define SBI_EXT_PMU_NUM_COUNTERS   0x0

◆ SBI_EXT_RFENCE

#define SBI_EXT_RFENCE   0x52464E43

◆ SBI_EXT_RFENCE_REMOTE_FENCE_I

#define SBI_EXT_RFENCE_REMOTE_FENCE_I   0x0

◆ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA

#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA   0x4

◆ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID

#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID   0x3

◆ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA

#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA   0x6

◆ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID

#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID   0x5

◆ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA

#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA   0x1

◆ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID

#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID   0x2

◆ SBI_EXT_SRST

#define SBI_EXT_SRST   0x53525354

◆ SBI_EXT_SRST_RESET

#define SBI_EXT_SRST_RESET   0x0

◆ SBI_EXT_SUSP

#define SBI_EXT_SUSP   0x53555350

◆ SBI_EXT_SUSP_SUSPEND

#define SBI_EXT_SUSP_SUSPEND   0x0

◆ SBI_EXT_TIME

#define SBI_EXT_TIME   0x54494D45

◆ SBI_EXT_TIME_SET_TIMER

#define SBI_EXT_TIME_SET_TIMER   0x0

◆ SBI_EXT_VENDOR_END

#define SBI_EXT_VENDOR_END   0x09FFFFFF

◆ SBI_EXT_VENDOR_START

#define SBI_EXT_VENDOR_START   0x09000000

◆ SBI_HSM_STATE_RESUME_PENDING

#define SBI_HSM_STATE_RESUME_PENDING   0x6

◆ SBI_HSM_STATE_START_PENDING

#define SBI_HSM_STATE_START_PENDING   0x2

◆ SBI_HSM_STATE_STARTED

#define SBI_HSM_STATE_STARTED   0x0

◆ SBI_HSM_STATE_STOP_PENDING

#define SBI_HSM_STATE_STOP_PENDING   0x3

◆ SBI_HSM_STATE_STOPPED

#define SBI_HSM_STATE_STOPPED   0x1

◆ SBI_HSM_STATE_SUSPEND_PENDING

#define SBI_HSM_STATE_SUSPEND_PENDING   0x5

◆ SBI_HSM_STATE_SUSPENDED

#define SBI_HSM_STATE_SUSPENDED   0x4

◆ SBI_HSM_SUSP_BASE_MASK

#define SBI_HSM_SUSP_BASE_MASK   0x7fffffff

◆ SBI_HSM_SUSP_NON_RET_BIT

#define SBI_HSM_SUSP_NON_RET_BIT   0x80000000

◆ SBI_HSM_SUSP_PLAT_BASE

#define SBI_HSM_SUSP_PLAT_BASE   0x10000000

◆ SBI_HSM_SUSPEND_NON_RET_DEFAULT

#define SBI_HSM_SUSPEND_NON_RET_DEFAULT   SBI_HSM_SUSP_NON_RET_BIT

◆ SBI_HSM_SUSPEND_NON_RET_LAST

#define SBI_HSM_SUSPEND_NON_RET_LAST   (SBI_HSM_SUSP_NON_RET_BIT | SBI_HSM_SUSP_BASE_MASK)

◆ SBI_HSM_SUSPEND_NON_RET_PLATFORM

#define SBI_HSM_SUSPEND_NON_RET_PLATFORM   (SBI_HSM_SUSP_NON_RET_BIT | SBI_HSM_SUSP_PLAT_BASE)

◆ SBI_HSM_SUSPEND_RET_DEFAULT

#define SBI_HSM_SUSPEND_RET_DEFAULT   0x00000000

◆ SBI_HSM_SUSPEND_RET_LAST

#define SBI_HSM_SUSPEND_RET_LAST   SBI_HSM_SUSP_BASE_MASK

◆ SBI_HSM_SUSPEND_RET_PLATFORM

#define SBI_HSM_SUSPEND_RET_PLATFORM   SBI_HSM_SUSP_PLAT_BASE

◆ SBI_PMU_CFG_FLAG_AUTO_START

#define SBI_PMU_CFG_FLAG_AUTO_START   (1 << 2)

◆ SBI_PMU_CFG_FLAG_CLEAR_VALUE

#define SBI_PMU_CFG_FLAG_CLEAR_VALUE   (1 << 1)

◆ SBI_PMU_CFG_FLAG_SET_MINH

#define SBI_PMU_CFG_FLAG_SET_MINH   (1 << 7)

◆ SBI_PMU_CFG_FLAG_SET_SINH

#define SBI_PMU_CFG_FLAG_SET_SINH   (1 << 6)

◆ SBI_PMU_CFG_FLAG_SET_UINH

#define SBI_PMU_CFG_FLAG_SET_UINH   (1 << 5)

◆ SBI_PMU_CFG_FLAG_SET_VSINH

#define SBI_PMU_CFG_FLAG_SET_VSINH   (1 << 4)

◆ SBI_PMU_CFG_FLAG_SET_VUINH

#define SBI_PMU_CFG_FLAG_SET_VUINH   (1 << 3)

◆ SBI_PMU_CFG_FLAG_SKIP_MATCH

#define SBI_PMU_CFG_FLAG_SKIP_MATCH   (1 << 0)

◆ SBI_PMU_CTR_TYPE_FW

#define SBI_PMU_CTR_TYPE_FW   1

◆ SBI_PMU_CTR_TYPE_HW

#define SBI_PMU_CTR_TYPE_HW   0

SBI PMU counter type

◆ SBI_PMU_EVENT_HW_CACHE_ID_MASK

#define SBI_PMU_EVENT_HW_CACHE_ID_MASK   0xfff8

◆ SBI_PMU_EVENT_HW_CACHE_ID_OFFSET

#define SBI_PMU_EVENT_HW_CACHE_ID_OFFSET   3

◆ SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK

#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK   0x6

◆ SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET

#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET   1

◆ SBI_PMU_EVENT_HW_CACHE_OPS_RESULT

#define SBI_PMU_EVENT_HW_CACHE_OPS_RESULT   0x1

◆ SBI_PMU_EVENT_IDX_CODE_MASK

#define SBI_PMU_EVENT_IDX_CODE_MASK   0xFFFF

◆ SBI_PMU_EVENT_IDX_INVALID

#define SBI_PMU_EVENT_IDX_INVALID   0xFFFFFFFF

◆ SBI_PMU_EVENT_IDX_MASK

#define SBI_PMU_EVENT_IDX_MASK   0xFFFFF

◆ SBI_PMU_EVENT_IDX_TYPE_MASK

#define SBI_PMU_EVENT_IDX_TYPE_MASK   (0xF << SBI_PMU_EVENT_IDX_TYPE_OFFSET)

◆ SBI_PMU_EVENT_IDX_TYPE_OFFSET

#define SBI_PMU_EVENT_IDX_TYPE_OFFSET   16

◆ SBI_PMU_EVENT_RAW_IDX

#define SBI_PMU_EVENT_RAW_IDX   0x20000

◆ SBI_PMU_EVENT_TYPE_FW

#define SBI_PMU_EVENT_TYPE_FW   0xf

◆ SBI_PMU_EVENT_TYPE_HW

#define SBI_PMU_EVENT_TYPE_HW   0x0

SBI PMU event idx type

◆ SBI_PMU_EVENT_TYPE_HW_CACHE

#define SBI_PMU_EVENT_TYPE_HW_CACHE   0x1

◆ SBI_PMU_EVENT_TYPE_HW_RAW

#define SBI_PMU_EVENT_TYPE_HW_RAW   0x2

◆ SBI_PMU_EVENT_TYPE_MAX

#define SBI_PMU_EVENT_TYPE_MAX   0x10

◆ SBI_PMU_FW_ACCESS_LOAD

#define SBI_PMU_FW_ACCESS_LOAD   2

◆ SBI_PMU_FW_ACCESS_STORE

#define SBI_PMU_FW_ACCESS_STORE   3

◆ SBI_PMU_FW_FENCE_I_RECVD

#define SBI_PMU_FW_FENCE_I_RECVD   9

◆ SBI_PMU_FW_FENCE_I_SENT

#define SBI_PMU_FW_FENCE_I_SENT   8

◆ SBI_PMU_FW_HFENCE_GVMA_RCVD

#define SBI_PMU_FW_HFENCE_GVMA_RCVD   15

◆ SBI_PMU_FW_HFENCE_GVMA_SENT

#define SBI_PMU_FW_HFENCE_GVMA_SENT   14

◆ SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD

#define SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD   17

◆ SBI_PMU_FW_HFENCE_GVMA_VMID_SENT

#define SBI_PMU_FW_HFENCE_GVMA_VMID_SENT   16

◆ SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD

#define SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD   21

◆ SBI_PMU_FW_HFENCE_VVMA_ASID_SENT

#define SBI_PMU_FW_HFENCE_VVMA_ASID_SENT   20

◆ SBI_PMU_FW_HFENCE_VVMA_RCVD

#define SBI_PMU_FW_HFENCE_VVMA_RCVD   19

◆ SBI_PMU_FW_HFENCE_VVMA_SENT

#define SBI_PMU_FW_HFENCE_VVMA_SENT   18

◆ SBI_PMU_FW_ILLEGAL_INSN

#define SBI_PMU_FW_ILLEGAL_INSN   4

◆ SBI_PMU_FW_IPI_RECVD

#define SBI_PMU_FW_IPI_RECVD   7

◆ SBI_PMU_FW_IPI_SENT

#define SBI_PMU_FW_IPI_SENT   6

◆ SBI_PMU_FW_MAX

#define SBI_PMU_FW_MAX   22

◆ SBI_PMU_FW_MISALIGNED_LOAD

#define SBI_PMU_FW_MISALIGNED_LOAD   0

Special "firmware" events provided by the OpenSBI, even if the hardware does not support performance events. These events are encoded as a raw event type in Linux kernel perf framework.

◆ SBI_PMU_FW_MISALIGNED_STORE

#define SBI_PMU_FW_MISALIGNED_STORE   1

◆ SBI_PMU_FW_PLATFORM

#define SBI_PMU_FW_PLATFORM   0xFFFF

◆ SBI_PMU_FW_RESERVED_MAX

#define SBI_PMU_FW_RESERVED_MAX   0xFFFE

◆ SBI_PMU_FW_SET_TIMER

#define SBI_PMU_FW_SET_TIMER   5

◆ SBI_PMU_FW_SFENCE_VMA_ASID_RCVD

#define SBI_PMU_FW_SFENCE_VMA_ASID_RCVD   13

◆ SBI_PMU_FW_SFENCE_VMA_ASID_SENT

#define SBI_PMU_FW_SFENCE_VMA_ASID_SENT   12

◆ SBI_PMU_FW_SFENCE_VMA_RCVD

#define SBI_PMU_FW_SFENCE_VMA_RCVD   11

◆ SBI_PMU_FW_SFENCE_VMA_SENT

#define SBI_PMU_FW_SFENCE_VMA_SENT   10

◆ SBI_PMU_HW_BRANCH_INSTRUCTIONS

#define SBI_PMU_HW_BRANCH_INSTRUCTIONS   5

◆ SBI_PMU_HW_BRANCH_MISSES

#define SBI_PMU_HW_BRANCH_MISSES   6

◆ SBI_PMU_HW_BUS_CYCLES

#define SBI_PMU_HW_BUS_CYCLES   7

◆ SBI_PMU_HW_CACHE_BPU

#define SBI_PMU_HW_CACHE_BPU   5

◆ SBI_PMU_HW_CACHE_DTLB

#define SBI_PMU_HW_CACHE_DTLB   3

◆ SBI_PMU_HW_CACHE_ITLB

#define SBI_PMU_HW_CACHE_ITLB   4

◆ SBI_PMU_HW_CACHE_L1D

#define SBI_PMU_HW_CACHE_L1D   0

Generalized hardware cache events:

  { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
  { read, write, prefetch } x
  { accesses, misses }

◆ SBI_PMU_HW_CACHE_L1I

#define SBI_PMU_HW_CACHE_L1I   1

◆ SBI_PMU_HW_CACHE_LL

#define SBI_PMU_HW_CACHE_LL   2

◆ SBI_PMU_HW_CACHE_MAX

#define SBI_PMU_HW_CACHE_MAX   7

◆ SBI_PMU_HW_CACHE_MISSES

#define SBI_PMU_HW_CACHE_MISSES   4

◆ SBI_PMU_HW_CACHE_NODE

#define SBI_PMU_HW_CACHE_NODE   6

◆ SBI_PMU_HW_CACHE_OP_MAX

#define SBI_PMU_HW_CACHE_OP_MAX   3

◆ SBI_PMU_HW_CACHE_OP_PREFETCH

#define SBI_PMU_HW_CACHE_OP_PREFETCH   2

◆ SBI_PMU_HW_CACHE_OP_READ

#define SBI_PMU_HW_CACHE_OP_READ   0

◆ SBI_PMU_HW_CACHE_OP_WRITE

#define SBI_PMU_HW_CACHE_OP_WRITE   1

◆ SBI_PMU_HW_CACHE_REFERENCES

#define SBI_PMU_HW_CACHE_REFERENCES   3

◆ SBI_PMU_HW_CACHE_RESULT_ACCESS

#define SBI_PMU_HW_CACHE_RESULT_ACCESS   0

◆ SBI_PMU_HW_CACHE_RESULT_MAX

#define SBI_PMU_HW_CACHE_RESULT_MAX   2

◆ SBI_PMU_HW_CACHE_RESULT_MISS

#define SBI_PMU_HW_CACHE_RESULT_MISS   1

◆ SBI_PMU_HW_CPU_CYCLES

#define SBI_PMU_HW_CPU_CYCLES   1

◆ SBI_PMU_HW_GENERAL_MAX

#define SBI_PMU_HW_GENERAL_MAX   11

◆ SBI_PMU_HW_INSTRUCTIONS

#define SBI_PMU_HW_INSTRUCTIONS   2

◆ SBI_PMU_HW_NO_EVENT

#define SBI_PMU_HW_NO_EVENT   0

General pmu event codes specified in SBI PMU extension

◆ SBI_PMU_HW_REF_CPU_CYCLES

#define SBI_PMU_HW_REF_CPU_CYCLES   10

◆ SBI_PMU_HW_STALLED_CYCLES_BACKEND

#define SBI_PMU_HW_STALLED_CYCLES_BACKEND   9

◆ SBI_PMU_HW_STALLED_CYCLES_FRONTEND

#define SBI_PMU_HW_STALLED_CYCLES_FRONTEND   8

◆ SBI_PMU_START_FLAG_SET_INIT_VALUE

#define SBI_PMU_START_FLAG_SET_INIT_VALUE   (1 << 0)

◆ SBI_PMU_STOP_FLAG_RESET

#define SBI_PMU_STOP_FLAG_RESET   (1 << 0)

◆ SBI_SPEC_VERSION_MAJOR_MASK

#define SBI_SPEC_VERSION_MAJOR_MASK   0x7f

◆ SBI_SPEC_VERSION_MAJOR_OFFSET

#define SBI_SPEC_VERSION_MAJOR_OFFSET   24

◆ SBI_SPEC_VERSION_MINOR_MASK

#define SBI_SPEC_VERSION_MINOR_MASK   0xffffff

◆ SBI_SRST_RESET_REASON_NONE

#define SBI_SRST_RESET_REASON_NONE   0x0

◆ SBI_SRST_RESET_REASON_SYSFAIL

#define SBI_SRST_RESET_REASON_SYSFAIL   0x1

◆ SBI_SRST_RESET_TYPE_COLD_REBOOT

#define SBI_SRST_RESET_TYPE_COLD_REBOOT   0x1

◆ SBI_SRST_RESET_TYPE_LAST

#define SBI_SRST_RESET_TYPE_LAST   SBI_SRST_RESET_TYPE_WARM_REBOOT

◆ SBI_SRST_RESET_TYPE_SHUTDOWN

#define SBI_SRST_RESET_TYPE_SHUTDOWN   0x0

◆ SBI_SRST_RESET_TYPE_WARM_REBOOT

#define SBI_SRST_RESET_TYPE_WARM_REBOOT   0x2

◆ SBI_SUCCESS

#define SBI_SUCCESS   0

◆ SBI_SUSP_PLATFORM_SLEEP_START

#define SBI_SUSP_PLATFORM_SLEEP_START   0x80000000

◆ SBI_SUSP_SLEEP_TYPE_LAST

#define SBI_SUSP_SLEEP_TYPE_LAST   SBI_SUSP_SLEEP_TYPE_SUSPEND

◆ SBI_SUSP_SLEEP_TYPE_SUSPEND

#define SBI_SUSP_SLEEP_TYPE_SUSPEND   0x0