Writing and Using LoongArch exception handlers in LARS
Introduction
Exception handlers, also known as trap handlers or
interrupt handlers, can easily be incorporated into a LoongArch program.
This guide is not intended to be comprehensive but provides the essential
information for writing and using exception handlers.
Although the same mechanism services all three, exceptions, traps
and interrupts are all distinct from each other.
Exceptions are caused by exceptional conditions that occur at runtime
such as invalid memory address references. Traps are caused by instructions
constructed especially for this purpose, listed below. Interrupts are
caused by external devices.
LARS partially but not completely implements the exception and interrupt
mechanism of LoongArch.
Essential Facts
Some essential facts about writing and using exception handlers include:
- LARS simulates basic elements of the LoongArch32 exception mechanism.
- When an exception occurs,
- Coprocessor 0 register $5 (ESTAT) bits 15-21 are set to the exception type (codes below)
- Coprocessor 0 register $6 (ERA) is set to the
address of the instruction that triggered the exception
- If the exception was caused by an invalid memory address,
Coprocessor 0 register $7 (BADV) is set to the invalid address.
- Execution flow jumps to the LoongArch
instruction at memory location 0x800000180. This address
in the kernel text segment (.ktext directive) is the
standard LoongArch32 exception handler location. The only way to change
it in LARS is to change the LoongArch memory configuration through
the Settings menu item Memory Configuration.
- There are three ways to include an exception handler in a LoongArch program
- Write the exception handler in the same file as the regular
program. An example of this is presented below.
- Write the exception handler in a separate file, store that file
in the same directory as the regular program, and select
the Settings menu item "Assemble all files in directory"
- Write the exception handler in a separate file, store that file
in any directory, then open the "Exception Handler..." dialog
in the Settings menu, check the check box and browse to
that file.
- If there is no instruction at location 0x800000180,
LARS will terminate the LoongArch program with an appropriate error message.
- The exception handler can return control to the program using
the eret instruction. This will place the ERA register $6 value into the
Program Counter, so be sure to increment $6 by 4 before returning
to skip over the instruction that caused the exception. The mfc0
and mtc0 instructions are used to read from and write to Coprocessor 0
registers.
- Bits 16-21 of the ESTAT register $5 can also be used to indicate
pending interrupts.
- Exception Ecodes declared in lars.simulator.Exceptions, but
not necessarily implemented, are
INTERRUPT=0X0;
PAGE_INTERRUPT_LOAD=0x1;
PAGE_INTERRUPT_STORE=0x2;
PAGE_INTERRUPT_FETCH=0x3;
PAGE_INTERRUPT_MODIFY=0x4;
PAGE_PLV_INTERRUPT=0x7;
ADDRESS_EXCEPTION_FETCH=0x8;
ADDRESS_EXCEPTION_MEMORY=0x8;
ALIGN_EXCEPTION=0x9;
SYSCALL_EXCEPTION=0xb;
BREAKPOINT_EXCEPTION = 0xc;
INSTRUCTION_NOT_EXIST=0xd;
INSTRUCTION_PLV_EXCEPTION=0xe;
FLOATING_POINT_DISABLE=0xf;
FLOATING_POINT_EXCEPTION=0x12;
TLB_REWRITE_EXCEPTION=0x3f;
- When writing a non-trivial exception handler, your handler must first save
general purpose register contents, then restore them before returning.