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feat: add multi-core CPU parallel support (SMP up to 8 cores)

啊对对队 requested to merge feature/multi-core into main

Implement per-CPU scheduling with work stealing and interrupt-safe synchronization primitives for RISC-V 64 (RV64GC, SV39).

Core changes:

  • sync/spin: SpinLock and SpinNoIrq (atomic + SIE disable)
  • cpu: hart detection, amoswap-based boot hart election, per-CPU processor array
  • entry.asm: multi-hart boot with per-CPU stacks and atomic boot flag
  • sbi: HSM (hart start/stop), IPI (send_ipi), RFENCE (tlb_shootdown) extensions
  • task: per-CPU ready queues, work stealing from boot hart, WFI idle
  • trap: kernel trap vector (timer/software interrupt handling)
  • secondary harts activate SV39 via shared kernel page table
  • kernel stack increased to 32KB for multi-core workloads
  • frame allocator: ppn=0 guard checks

Verified: SMP=1/2/4/8 all pass usertests and benchmark suites.

Co-Authored-By: Claude Opus 4.7 noreply@anthropic.com

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