ASM.hpp

#pragma once

#include "IR/IR.hpp"
#include "Util/List.hpp"

#include <cassert>
#include <utility>
#include <variant>
#include <vector>
#include <map>

namespace SyOC::ARMv7a {



struct Register {
  enum IntRegs {
#define FirstIntReg(x) INTEGER_REG_BEGIN = x,
#define TargetIntegralRegister(x, y, z) x = z,
#define LastIntReg(x) INTEGER_REG_END = x,
#include "Common/TargetInfo.def"
  };
  enum VFPRegs {
#define FirstVFPReg(x) VFP_REG_BEGIN = x,
#define TargetFloatRegister(x, y, z) x = z,
#define LastVFPReg(x) VFP_REG_END = x,
#include "Common/TargetInfo.def"
  };
  enum StatusRegs {
#define FirstStatusReg(x) STATUS_REG_BEGIN = x,
#define TargetStatusRegister(x, y, z) x = z,
#define LastStatusReg(x) STATUS_REG_END = x,
#include "Common/TargetInfo.def"
  };
  enum VirtualRegs {
#define FirstVirtualReg(x) VREG_BEGIN = x,
#include "Common/TargetInfo.def"
  };
  enum Type {
    Int,
    Float,
  };
  int id = -1;
  Type type = Int;

  inline bool isInvalid() const { return id == -1; }
  inline bool isVirtual() const { return !(isInteger() || isFloat() || isStatus()) && id > 0; }
  inline bool isInteger() const { return id >= INTEGER_REG_BEGIN && id <= INTEGER_REG_END; }
  inline bool isFloat() const { return id >= VFP_REG_BEGIN && id <= VFP_REG_END; }
  inline bool isStatus() const { return id >= STATUS_REG_BEGIN && id <= STATUS_REG_END; }
};

struct RegisterList {
  typedef uint32_t RegVector;
  static const int RegCount = 32;
  RegVector ls = 0; // vmov, vpush requires 32 bit.
  // std::bitset<RegCount> ls;
};

struct FrameObject {
  int32_t Offset;
  size_t Size;
  const Instruction* Alloca;
  bool isSpill;
  FrameObject(int32_t Offset, size_t Size,
              Instruction *Alloca = nullptr, bool isSpill = false) :
    Offset(Offset), Size(Size), Alloca(Alloca), isSpill(isSpill) { }
};

// llvm MachineFrameInfo.