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王卓然 authoredec9bf883
.arch armv8-a
.file ""
.text
.global main
.arm
.fpu neon
.global_vars:
main:
@ thread_stack_size=128
@ stack_size=40140
.main_pre:
@ function preprocess
@ enlarge stack
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
movw r0, #0
movt r0, #4096
mov r1, #1
bl malloc
movw r11, #0
movt r11, #4096
add r12, r0, r11
pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
mov r11, sp
mov sp, r12
push {r11}
@ save callee-save registers and lr
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@ allocate stack space
mov r11, #40140
sub sp, sp, r11
@ process function args
.main_entry:
@ [ 10000 x i32]* %0 = Alloca
add r4, sp, #128
push {r0, r1, r2, r3}
mov r0, r4
mov r1, #0
mov r2, #40000
bl memset
pop {r0, r1, r2, r3}
@ [ 3 x i32]* %1 = Alloca
mov r11, #40128
add r0, sp, r11
push {r0, r1, r2, r3}
mov r1, #0
mov r2, #12
bl memset
pop {r0, r1, r2, r3}
@ Store i32 19971231 [ 3 x i32]* %1
movw r12, #48287
movt r12, #304
str r12, [r0, #0]
@ Store i32 19981013 [ 3 x i32]* %1 i32 4
movw r12, #58069
movt r12, #304
str r12, [r0, #4]
@ Store i32 1000000007 [ 3 x i32]* %1 i32 8
movw r12, #51719
movt r12, #15258
str r12, [r0, #8]
@ i32 %2 = Call getint
push {r0, r4}
bl getint
mov r1, r0
pop {r0, r4}
@ i32 %3 = Call getint
push {r0, r1, r4}
bl getint
mov r2, r0
pop {r0, r1, r4}
7172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140
@ Call _sysy_starttime i32 1
push {r0, r1, r2, r3}
mov r0, #1
bl _sysy_starttime
pop {r0, r1, r2, r3}
@ i32 %4 = Load [ 3 x i32]* %1
ldr r6, [r0, #0]
@ i32 %5 = Load [ 3 x i32]* %1 i32 4
ldr r5, [r0, #4]
@ i32 %6 = Load [ 3 x i32]* %1 i32 8
ldr r0, [r0, #8]
@ Br <label> %7
.main_entry_branch_1:
@ %8 <= %3
@ %9 <= %2
@ branch instruction eliminated
.main_7:
@ i32 %8 = PHI i32 %3 <label> %entry i32 %30 <label> %29
@ i32 %9 = PHI i32 %2 <label> %entry i32 %11 <label> %29
@ Br GT i32 %9 i32 0 <label> %10 <label> %41
cmp r1, #0
ble .main_41+0
.main_7_branch_1:
@ branch instruction eliminated
.main_7_branch_2:
@ branch instruction eliminated
.main_10:
@ i32 %11 = Sub i32 %9 i32 1
sub r7, r1, #1
@ i32 %12 = MulAdd i32 %8 i32 %4 i32 %5
mla r1, r2, r6, r5
@ i32 %13 = Div i32 %12 i32 %6
sdiv r2, r1, r0
@ i32 %14 = Mul i32 %13 i32 %6
mul r2, r2, r0
@ i32 %15 = Sub i32 %12 i32 %14
sub r1, r1, r2, lsl #0
@ Br LT i32 %15 i32 0 <label> %16 <label> %18
cmp r1, #0
bge .main_18+0
.main_10_branch_1:
@ branch instruction eliminated
.main_10_branch_2:
@ %19 <= %15
@ branch instruction eliminated
.main_16:
@ i32 %17 = Add i32 %6 i32 %15
add r1, r0, r1, lsl #0
@ Br <label> %18
.main_16_branch_1:
@ %19 <= %17
@ branch instruction eliminated
.main_18:
@ i32 %19 = PHI i32 %15 <label> %10 i32 %17 <label> %16
@ i32 %20 = Div i32 %19 i32 300000
movw r11, #7557
movt r11, #28633
smmul r11, r11, r1
asr r11, r11, #17
add r2, r11, r1, lsr #31
@ i32 %21 = Mul i32 %20 i32 300000
movw lr, #37856
movt lr, #4
mul r2, r2, lr
@ i32 %22 = Sub i32 %19 i32 %21
sub r3, r1, r2, lsl #0
@ i32 %23 = MulAdd i32 %19 i32 %4 i32 %5
mla r1, r1, r6, r5
@ i32 %24 = Div i32 %23 i32 %6
sdiv r2, r1, r0