- 27 Feb, 2023 35 commits
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Marco Elver authored
During legalization of the SelectionDAG, some nodes are replaced with arch-specific nodes. These may be complex nodes, where the root node no longer corresponds to the node that should carry the extra info. Fix the issue by copying extra info to the new node and all its new transitive operands during RAUW. See code comments for more details. This fixes the remaining pcsections-atomics.ll tests on X86. Reviewed By: dvyukov Differential Revision: https://reviews.llvm.org/D144677
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Marco Elver authored
Use MIMetadata() to propagate both DebugLoc and !pcsections metadata. This fixes several of the non-native sized !pcsections tests in pcsections-atomics.ll. Reviewed By: dvyukov Differential Revision: https://reviews.llvm.org/D144676
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Marco Elver authored
Extend pcsections-atomics.ll to exhaustively test all atomic ops up to 64 bits. This currently shows that some atomic operations do not end up in PC sections. This will be addressed in a subsequent change. Differential Revision: https://reviews.llvm.org/D144710
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Marco Elver authored
The pcsections.ll test primarily tests that the AsmPrinter produces the right output in sections. This output is not easily covered by update_llc_test_checks.py, and as such is hand written. This makes maintenance rather burdensome. Instead, let's keep pcsections.ll as simple as possible. Move the more complex tests that primarily test that some atomic operations end up in the PC section to pcsections-atomics.ll. NFC. Reviewed By: dvyukov, vitalybuka Differential Revision: https://reviews.llvm.org/D144675
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Nikita Popov authored
This addresses the compile-time regression reported on D144369. If we don't fold constant operands early, then we might end up walking very large use lists of constants here. Explicitly exclude constants, and also limit the number of inspected users to avoid degenerate cases like this. This entire transform shouldn't be part of InstCombine in the first place though.
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Manuel Klimek authored
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chendewen authored
[SVE] Add intrinsics for uniform dsp operations that explicitly undefine the result for inactive lanes. This patch adds new intrinsics for uniform dsp operations and changes the lowering for the following builtins to emit calls to the new aarch64.sve.###.u intrinsics. svsqsub_x svsqsub_n_x svuqsub_x svuqsub_n_x svsqsubr_x svsqsubr_n_x svuqsubr_x svuqsubr_n_x Reviewed By: Paul Walker Differential Revision: https://reviews.llvm.org/D144704
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Manuel Klimek authored
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Haojian Wu authored
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Michael Platings authored
This is important for building runtimes for bare metal targets. Differential Revision: https://reviews.llvm.org/D144757
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Max Kazantsev authored
Details: https://github.com/llvm/llvm-project/issues/61022
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Sergey Kachkov authored
This reverts commit b5bf6f63.
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Nikita Popov authored
Represent scalable type sizes using C * vscale, where vscale is the vscale constant expression. This exposes a bit more information to SCEV, because the vscale multiplier is explicitly modeled in SCEV (rather than part of the sizeof expression). This is mainly intended as an alternative to D143642. Differential Revision: https://reviews.llvm.org/D144624
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Augustin Fabre authored
Differential Revision: https://reviews.llvm.org/D143560
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LLVM GN Syncbot authored
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Carlos Alberto Enciso authored
llvm-debuginfo-analyzer is a command line tool that processes debug info contained in a binary file and produces a debug information format agnostic “Logical View”, which is a high-level semantic representation of the debug info, independent of the low-level format. The code has been divided into the following patches: 1) Interval tree 2) Driver and documentation 3) Logical elements 4) Locations and ranges 5) Select elements 6) Warning and internal options 7) Compare elements 8) ELF Reader 9) CodeView Reader Full details: https://discourse.llvm.org/t/llvm-dev-rfc-llvm-dva-debug-information-visual-analyzer/62570 This patch: This is a high level summary of the changes in this patch. CodeView Reader - Support for CodeView/PDB. LVCodeViewReader, LVTypeVisitor, LVSymbolVisitor, LVLogicalVisitor Reviewed By: psamolysov, probinson, djtodoro, zequanwu Differential Revision: https://reviews.llvm.org/D125784
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Haojian Wu authored
incompatible flags in the CLI tool.
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Sergey Kachkov authored
Process cases when phi incoming in predecessor block has select instruction, and this select address is unavailable, but there are addresses translated from both sides of select instruction. Differential Revision: https://reviews.llvm.org/D142705
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Christian Ulmann authored
This commit ensures that no empty debug metadata strings are exported as these are not legal names. Additionally, this commit ensures that non-existing strings are not accidentially imported as empty strings. Reviewed By: gysit Differential Revision: https://reviews.llvm.org/D144263
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Diana Picus authored
Update a few tests where the checks aren't exactly kosher. Differential Revision: https://reviews.llvm.org/D144639
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Christian Ulmann authored
Reviewed By: gysit Differential Revision: https://reviews.llvm.org/D144267
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Matthias Springer authored
Incorrect API usage was detected by D144552. Differential Revision: https://reviews.llvm.org/D144636
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Jean Perier authored
- always use genExprAddr when lowering to HLFIR: it does not create temporary for array sections without vector subscripts, so there is no need to have custom logic. - update mangling to deal with AssocDetailsEntity. Their name is required in HLFIR so that it can be added to the hlfir.declare that is created for the selector once it is lowered. This should allow getting debug info for selector when debug info are generated from hlfir.declare. The rest of associate construct lowering is unchanged and shared with the current lowering. This patch also enables select type lowering to work properly, but some other todos (mainly about parent component references) prevents porting the tests for now, so this will be done later. Differential Revision: https://reviews.llvm.org/D144740
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Jean Perier authored
Nothing much to do except set the right attributes on hlfir.assign. Differential Revision: https://reviews.llvm.org/D144727
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Jean Perier authored
Differential Revision: https://reviews.llvm.org/D144723
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Nilanjana Basu authored
Inserting scalar result of 'uaddlv' neon intrinsic function to a destination vector currently makes use of the integer unit. Subsequent patches will eliminate the redundant use of the integer registers in a more generic way that will include this special case. This is an initial set of tests for this functionality. Differential Revision: https://reviews.llvm.org/D143038
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Lei Zhang authored
We use `use64bitIndex` in the option to decide the target device address bitwidth. This makes it consistent with index type conversion too. Reviewed By: kuhar Differential Revision: https://reviews.llvm.org/D144827
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Lei Zhang authored
Vulkan requires GPU processor ID/count builtin variables to be 32-bit scalar or vector for all the cases. Similarly there are special requirements for OpenCL. We need to make sure those rules are respected when converting using 64bit for index. Reviewed By: kuhar Differential Revision: https://reviews.llvm.org/D144819
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Rahul Kayaith authored
The asm printer grew the ability to automatically fall back to the generic format for invalid ops, so this logic doesn't need to be in the bindings anymore. The printer already handles supressing diagnostics that get emitted while checking if the op is valid. Reviewed By: mehdi_amini, stellaraccident Differential Revision: https://reviews.llvm.org/D144805
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Jun Zhang authored
Signed-off-by:
Jun Zhang <jun@junz.org>
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Serge Pavlov authored
If a template function contained a pragma that made it strictfp, code generation for such function crashed, because the instantiation did not have strictfp attribute. As a solution this attribute is copied from the template to instantiation. Differential Revision: https://reviews.llvm.org/D143919
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Craig Topper authored
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Jie Fu authored
/data/llvm-project/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp:1200:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] case X86II::RawFrm: ^
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Shengchen Kan authored
1. Add a variable `HasRegOp` to record if the instruction has a register operand 2. Enumerate all the formats with a register operand in the switch 2. Add a default (unreachable) label in the switch (suggested by @reames) Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D144776
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Craig Topper authored
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- 26 Feb, 2023 5 commits
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Amara Emerson authored
We use this combine in the AArch64 postlegalizer combiner, which causes this function to query the legalizer rules for the action for an invalid opcode/type combination (G_AND and p0). Moving the legalizer query until after the validity check in matchHoistLogicOpWithSameOpcodeHands() fixes this.
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isuckatcs authored
This patch implements the exception handling rules found in N4849 14.4 and as a result fixes many false positives in the bugprone-exception-escape checker. Differential Revision: https://reviews.llvm.org/D135495
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Lei Zhang authored
This commit just adds options to control index type bitwidth in GPUToSPIRV conversion, and updates tests to prepare for 64bit index conversion. Reviewed By: kuhar Differential Revision: https://reviews.llvm.org/D144826
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LLVM GN Syncbot authored
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Nico Weber authored
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