Skip to content
GitLab
Explore
Projects
Groups
Topics
Snippets
Projects
Groups
Topics
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
educg-net-26173-2487151
sysy-compiler-1811
Commits
679d36a7
Commit
679d36a7
authored
7 months ago
by
noveky
Browse files
Options
Download
Plain Diff
Merge branch 'main' of
https://gitlab.eduxiji.net/T202410486202978/sysy-compiler
parents
d4720907
da8775a1
main
submit0820
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
src/midend/analyses/LoopIndVar.cpp
+1
-1
src/midend/analyses/LoopIndVar.cpp
with
1 addition
and
1 deletion
+1
-1
src/midend/analyses/LoopIndVar.cpp
+
1
−
1
View file @
679d36a7
...
...
@@ -120,7 +120,7 @@ void LoopInductionVariableAnalysis::findIndVar(Ptr<Loop> loop) {
if
(
auto
operInst
=
castPtr
<
OperInst
>
(
inst
))
{
if
(
operInst
->
isBinary
()
&&
(
operInst
->
op
()
==
OperInst
::
Operator
::
Add
||
operInst
->
op
()
==
OperInst
::
Operator
::
Sub
||
operInst
->
op
()
==
OperInst
::
Operator
::
Mul
||
operInst
->
op
()
==
OperInst
::
Operator
::
Div
))
{
// 检查操作数是否为归纳变量和循环不变量的组合
if
(
this
->
invariantCtx
->
isInvariant
(
operInst
->
lhs
()))
{
if
(
this
->
invariantCtx
->
isInvariant
(
operInst
->
lhs
())
&&
operInst
->
rhs
().
isRegister
()
)
{
auto
rhsReg
=
operInst
->
rhs
().
getRegister
();
if
(
indVars
.
find
(
rhsReg
)
!=
indVars
.
end
())
{
// 将新发现的归纳变量加入集合
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Supports
Markdown
0%
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment
Menu
Explore
Projects
Groups
Topics
Snippets